//Distributed with permission from Xilinx, Inc.

`timescale 1ns / 10ps

//-----------------------------------------------------------------------------
// VccAuxFix.v
//-----------------------------------------------------------------------------

module VccAuxFix (clk_in, busy);
  input clk_in;
  output busy;

  wire busy; 
  wire [7:0] rom_data;
  wire [7:0] gnd = 8'b0;

  reg icap_ce, done;
  reg [4:0] rom_addr;

  //synthesis attribute INIT of rom_addr is 0;
  //synthesis attribute INIT of done is 0;

  always @(posedge clk_in)
    if (done) icap_ce <= 1;
    else if (busy) icap_ce <= 0;
    else icap_ce <= 1;

  always @(posedge clk_in)
    if (! icap_ce && ! done) rom_addr <= rom_addr + 1;

  always @(posedge clk_in)
    if (rom_addr == 5'b10110) done <= 1;  // stop two before actually done

  RAM32X8S RAM32X8S_inst (
     .D(gnd),
     .WCLK(clk_in),
     .WE(gnd[0]),
     .O(rom_data),      // RAM output
     .A0(rom_addr[0]),  // RAM address[0] input
     .A1(rom_addr[1]),  // RAM address[1] input
     .A2(rom_addr[2]),  // RAM address[2] input
     .A3(rom_addr[3]),  // RAM address[3] input
     .A4(rom_addr[4])   // RAM address[3] input
  );

  defparam RAM32X8S_inst.INIT_00 = 32'h0000403f;
  defparam RAM32X8S_inst.INIT_01 = 32'h000000cf;
  defparam RAM32X8S_inst.INIT_02 = 32'h0010119f;
  defparam RAM32X8S_inst.INIT_03 = 32'h0000106f;
  defparam RAM32X8S_inst.INIT_04 = 32'h0000003f;
  defparam RAM32X8S_inst.INIT_05 = 32'h000800cf;
  defparam RAM32X8S_inst.INIT_06 = 32'h0000009f;
  defparam RAM32X8S_inst.INIT_07 = 32'h0000806f;

  ICAP_VIRTEX4 ICAP_VIRTEX4_inst (
    .BUSY(busy),          // Busy output
    .O(),                 // 32-bit data output
    .CE(icap_ce),         // Clock enable input
    .CLK(clk_in),         // Clock input
    .I({24'b0,rom_data}), // 32-bit data input
    .WRITE(gnd[0])        // Write input
  );
      
  defparam ICAP_VIRTEX4_inst.ICAP_WIDTH = "X8"; // "X8" or "X32"

// synthesis attribute LOC of ICAP_VIRTEX4_inst is ICAP_X0Y1;

  STARTUP_VIRTEX4 STARTUP_VIRTEX4_inst (
    .CLK(clk_in),
    .GSR(),
    .GTS(),
    .USRCCLKO(),
    .USRCCLKTS(),
    .USRDONEO(),
    .USRDONETS(),
    .EOS()
  );

endmodule